1. Field
Embodiments of the present invention relate to hot-plug technology and, in particular, to peripheral component interconnect (PCI) standard hot-plug controllers.
2. Discussion of Related Art
A peripheral component interconnect (PCI) bus is a bus in a computer system that interconnects a microprocessor and peripheral devices, such as keyboards, disk drives, video adapters, etc. A PCI bus has slots into which the adapter cards for the peripheral devices can be inserted or removed. Hot-plug technology allows a user to physically remove or insert one or more PCI adapter cards without having to remove power to the entire system or re-booting the system software. Only the individual PCI slots are affected and the other devices in the system are not disrupted.
Hot-plug controllers were being developed by various vendors that were compatible with the PCI Hot-Plug Specification, Revision 1.0, Oct. 6, 1997, PCI Special Interest Group, Portland, Oreg. It has been proposed that standardized hot-plug controllers be developed so that vendor-specific hot-plug controllers could be compatible across many platforms. The PCI Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0, Jun. 20, 2001, PCI Special Interest Group, Portland, Oreg., (hereinafter “SHPC Specification”) was developed to meet this challenge.
The SHPC Specification provides several commands that may be implemented for insertion and removal of adapter cards. One command may be a “PWRONLY” command, which instructs the SHPC to power up one or more target PCI slots without connecting clock or bus signals to the slots. Another command may be an “ENABLE” command, which instructs the SHPC to power up one or more target PCI slots, and to connect the clock and bus signals. Another command may be a “DISABLE” command, which instructs the SHPC to disconnect power, clock, and bus signals from one or more target PCI slots. Another command may be a “SET BUS SEGMENT SPEED” command, which instructs the SHPC to change the speed of the PCI bus.
The SHPC Specification provides that the application of power to the PCI bus be in strict accordance with the timing specification provided therein. The enabling of the bus and clocks on the PCI bus must be in strict accordance with the timing specification as well.
The device supporting the SHPC typically provides several control signals to the SHPC, such as a signal to control the power state of one or more target PCI slots (e.g., PWREN), a signal to control the connection of the PCI clock to one or more target PCI slots (e.g., CLKEN), a signal to control the connection of various bus signals to one or more target PCI slots (e.g., BUSEN), a signal to reset one or more target PCI slots (e.g., RST), and/or a signal indicating that state of rail power to a target PCI slot (e.g. CARD PWR). When the SHPC is executing a command, such as PWRONLY, ENABLE, DISABLE, etc., the signals provided to the SHPC are asserted in a signal sequence. The time delay between assertion (or de-assertion) of one signal and assertion (or de-assertion) of another signal is referred to herein as a timing parameter.
The SHPC designer selects a value for each timing parameter. Selecting only one value for a timing parameter introduces a problem, however. All products and platforms that utilize the SHPC must conform to the value selected.